As a verification engineer with a knowledge of subsystems and SoCs, you will make valuable contributions to a team tasked with verifying functional correctness of the design under test.

Job Responsibilities:

• -> Build functional verification strategies, writing test plans, defining test methodologies, improving the verification methodologies, completing functional verification to the required quality levels and schedules.
• -> Working with project management on planning tasks, setting schedules, quality checkpoints, engineer will be fully responsible for the area of verification.
• -> Will collaborate with engineers from architecture, design, verification, implementation, modelling, performance analysis, silicon validation, FPGA and board development.
• -> Senior engineers are also encouraged to support junior members.

Requirements:

• -> Worked on embedded C based SoC verification environments
• -> Knowledge of assembly language, C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
• -> Experienced in one or more of various verification methodologies – UVM/OVM/eRM, formal, low power, emulation
• -> Exposure to all stages of verification: requirements collection, creation of verification methodology plans, testplans, testbench implementation, Testcases development, coverage closure, documentation and support
• -> Understanding of the fundamentals of system architectures